APPLICATION ENGINEER MANAGER

Application Engineer Manager - This is a great opportunity. Manage a team of Field Application Engineers to understand the customers' key concerns and provide guidance on the best technologies and methodologies to deploy to enable their success. Responsible for overseeing teams on the areas of:Simulation Xcelium Verification Methodologies: UVM, MDV, ABV, regressions, Vmanager Emulation on Palladium and prototyping with Protium Jasper Formal Help Cadence customers effectively deploy our industry leading verification products to the worlds top Semiconductor and System companies. Ramp up on functional verification and system validation spaces which are the fastest growing segments in semiconductor design industry, being responsible for engagements. Provide technical support in the Pre and Post-Sales process and will work with the FAE and account team to come up with innovative solutions to address our customers most challenging problems. Engage and lead AE team on Pre-sales technical campaigns from the technical side, working along with Sales and Marketing. Provide world-class proactive support, training, and problem consultation to make our users successful. Conduct root cause analysis and provide resolution to customer technical issues. Collaborate with R&D on: Simulation, Emulation, prototyping and formal areas. Help R&D and product engineers develop competitive and creative technical solutions. Understand the competitive landscape and continuously work on differentiating Cadences solutions. Minimum Requirements BSE or graduation in related areas. Track record of experience leading a technical team. Excellent RTL understanding and coding. 6+ years of experience in functional verification. Knowledge of Unix, C/C++. A strong interest in contributing to customer success with related technical interest in EDA, HDLs, and Logic Design. Excellent English written and oral communication skills. Nice to have skills Design fundamentals such as architecture, micro-architecture, HDLs synthesis, and timing. Verification skills such as UVM testbench architecture, development and debug, SystemVerilog, SVAF. Fundamental SoC architecture knowledge. Embedded software development and HW/SW co-design and co-verification. Some knowledge of formal verification technologies. Scripting languages such as Perl, Python, TCL, Bash. Additional Job Details: Employment category: CLTEmployment term: 40 hours/weekLocation: Av. do Contorno, 5800 - Savassi, Belo Horizonte, Minas Gerais, Brazil. About Cadence Design Systems: Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access our website. Were doing work that matters. Help us solve what others cant. #J-18808-Ljbffr